Answer:
a) 0.667
b) Yes
Explanation:
Data provided in the question:
Mean = 0.04 chip
Standard deviation, s = 0.003 chip
Lower Specification Limit, LSL = 0.034
Upper Specification Limit, USL = 0.046
Now,
a) Capability Index = ( USL - LSL ) ÷ ( 6 × s )
or
Capability Index = ( 0.046 - 0.034 ) ÷ ( 6 × 0.003 )
= 0.667
b) Cpk = min( [( USL - Mean) ÷ ( 3s ) , ( Mean - LSL) ÷ ( 3s ))
or
Cpk = min( ( 0.046 - 0.04) ÷ (3 × 0.003 ), ( 0.04 - 0.034 ) ÷ ( 3 × 0.003 ))
or
Cpk = min( ( 0.046 - 0.04) ÷ (3 × 0.003 ), ( 0.04 - 0.034 ) ÷ ( 3 × 0.003 ))
or
Cpk = min( 0.667, 0.667 )
Therefore,
Cpk = 0.667
as Cp and Cpk are equal
Hence, it is ideal condition and process is capable
